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CY7C131E-55NXI

Product Category: Memory
Manufacturer: Cypress Semiconductor
Description: SRAM 8Kb (1Kb x 8) 55ns Dual-Port SRAM
  datasheetCY7C131E-55NXI  Datasheet
Package:
Quantity: 96 PCS
Lead Free Status / RoHS Status: Lead free / RoHS Compliant
Lead Time: one to seven days
Click buy button to purchase: Buy
PRODUCT DETAILS

DESCRIPTION

CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be used as a standalone dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.


APPLICATION

functional description

CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be used as a standalone dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. The BUSY flag signals that the port is trying to access the same location, which is currently being accessed by the other port. The INT is an interrupt flag indicating that data is placed in a unique location[1]. The BUSY and INT flags are push pull outputs. An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.

The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP.


FEATURES

■ True dual-ported memory cells, which allow simultaneous

reads of the same memory location

■ 1 K / 2 K × 8 organization

■ 0.35 micron complementary metal oxide semiconductor

(CMOS) for optimum speed and power

■ High speed access: 15 ns

■ Low operating power: ICC = 110 mA (typical),

Standby: ISB3 = 0.05 mA (typical)

■ Fully asynchronous operation

■ Automatic power-down

■ BUSY output flag to indicate access to the same location by

both ports

■ INT flag for port-to-port communication

■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin

plastic quad flat package (PQFP)

■ Pb-free packages available


SPECIFICATION



 ManufacturerCypress Semiconductor
 Product CategoryMemory



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PICTURE


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CY7C131E-55NXI image

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